10 kW
Vin
FCX491A
UC9246
ToPowerStage
+3.3V
+1.8V
0.1 Fm
4.7 Fm
V33FB
V33A
V33D
BPCap
0.1 Fm
UCD9246
SLVSA34 –JANUARY 2010
www.ti.com
Some circuits in the device require 1.8V that is generated internally from the 3.3V supply. This voltage requires a
0.1 µF to 1 µF bypass capacitor from BPCap to ground.
Figure 6. 3.3V Shunt Regulator Controller I/O
Power On Reset
The UCD9246 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the
POR circuit detects the V33D rise. When V33D is greater than V
RESET
, the device initiates an internal startup
sequence. At the end of the delay sequence, the device begins normal operation, as defined by the downloaded
device PMBus configuration.
External Reset
The device can be forced into the reset state by an external circuit connected to the nRESET pin. A logic low
voltage on this pin holds the device in reset. To avoid an erroneous trigger caused by noise, a 10 kΩ pull up
resistor to 3.3V is recommended.
Output Voltage Adjustment
The nominal output voltage is programmed by a combination of PMBus commands: VOUT_COMMAND,
VOUT_CAL_OFFSET, VOUT_SCALE_LOOP, and VOUT_MAX. Their relationship is shown in Figure 7. These
PMBus parameters need to be set such that the resulting Vref DAC value does not exceed the maximum value
of V
ref
.
Output voltage margining is configured by the VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW commands.
The OPERATION command selects between the nominal output voltage and either of the margin voltages. The
OPERATION command also includes an option to suppress certain voltage faults and warnings while operating
at the margin settings.
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