Miele T 9246 C Specifications download pdf (Page 26)

UCD9246

SLVSA34 –JANUARY 2010

www.ti.com

When a voltage rail is in its idle state, the DPWM and SRE outputs are disabled, and the differential voltage on

the EAP/EAN pins are monitored by the controller. During idle the Vref DAC is adjusted to minimize the error

voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the

start ramp from that voltage with a minimum of disturbance. This is done by calculating the duty cycle that is

required to match the measured voltage on the rail. Nominally this is calculated as Vout / Vin. If the pre-bias

voltage on the output requires a smaller pulse width than the driver can deliver, as defined by the

DRIVER_MIN_PULSE PMBus command, then the start ramp is delayed until the internal ramp reference voltage

has increased to the point where the required duty cycle exceeds the specified minimum duty.

Once a soft start/stop ramp has begun, the output is controlled by adjusting the Vref DAC at a fixed rate and

allowing the digital compensator control engine to generate a duty cycle based on the error. The Vref DAC

adjustments are made at a rate of 10 kHz and are based on the TON_RISE or TOFF_FALL PMBus configuration

parameters.

Although the presence of a pre-bias voltage or a specified minimum DPWM pulse width affects the time when

the DPWM and SRE signals become active, the time from when the controller starts processing the turn-on

command to the time when it reaches regulation is TON_DELAY plus TON_RISE, regardless of the pre-bias or

minimum duty cycle.

During a normal ramp (i.e. no tracking, no current limiting events and no EADC saturation), the set point slews at

a pre-calculated rate based on the commanded output voltage and TON_RISE. Under closed loop control, the

compensator follows this ramp up to the regulation point.

Because the EADC in the controller has a limited range, it may saturate due to a large transient during a

start/stop ramp. If this occurs, the controller overrides the calculated set point ramp value, and adjusts the

reference DAC in the direction to minimize the error. It continues to step the reference DAC in this direction until

the EADC comes out of saturation. Once it is out of saturation, the start ramp continues, but from this new set

point voltage; and therefore, has an impact on the ramp time.

Voltage Tracking

Each voltage rail can be configured to operate in a tracking mode. When a voltage rail is configured to track

another voltage rail, it adjusts the set point to follow the master, which can be either another internal rail or the

external Vtrack pin. As in standard non-tracking mode, a target Vout is still specified for the voltage rail. If the

tracking input exceeds this target, the tracking voltage rail stops following the master signal, switches to

regulation gains, and regulates at the target voltage. When the tracking input drops below the target with 20 mV

of hysteresis, start-stop gains are re-loaded and the voltage rail follows the tracking reference. Note that the

target can be set above the range of the tracking input, forcing the voltage rail to always remain in tracking mode

with the start-stop gain.

During tracking, the Vref DAC is permitted to change only as fast as is possible without inducing the EADC to

saturate. This limit may be reached if the master ramps at an extremely fast rate, or if the master is at a

significantly different voltage when the rail is turned on. A current limit (current foldback) or the detection of the

EADC saturating will force the rail to temporarily deviate from the tracking reference. This behavior is the same in

normal regulation mode.

The PMBus command TRACKING_SOURCE is available to enable tracking mode and select the master to track.

The tracking mode is set individually for each rail, allowing each rail to have a different master, multiple rails to

share a master, or some rails to track while others remain independent. Additionally,

TRACKING_SCALE_MONITOR permits tracking at voltage with a fixed ratio to a master voltage. For example, a

ratio of 0.5 causes the rail to regulate at one half of the master’s voltage.

Sequencing

There are three methods to sequence voltage rails controlled by the UCD9246 that allow for a variety of system

sequencing configurations. Each of these options is configurable in the GUI. These methods include:

1. Use the PMBus to set the soft start/stop parameters for each rail. Multiple start/stop sequences may be

triggered simultaneously. Each voltage rail performs its sequencing in an open-loop manner. If any rail fails

to complete its sequence, all other rails are unaffected.

2. Daisy-chain the Power Good output signal from one controller to the PMBus_Cntl input on another.

3. Use the GPIO_SEQ_CONFIG command to assign dependencies between rails, or to configure unused pins

as sequencing control inputs or sequencing status outputs.

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Miele T 9246 C Specifications Page 26

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